SAPTARSHI DAS // EE · SYSTEMS
KERR SINGULARITY // CLICK & DRAG TO ROTATE // HOVER TO ACCELERATE

SAPTARSHI DAS

BRIDGING SILICON & SOFTWARE

ENTER SYSTEM ↓
⏣ EVENT HORIZON PENETRATED // ENTERING SYSTEM ARCHITECTURE
// 02 — ARCHITECT IDENTITY THE PERSON BEHIND THE SYSTEM
ACTIVE // INDIA
Saptarshi Das — Electrical & Computer Science Engineering

I build systems where physical electrons, firmware, and algorithms meet.

I am an Electrical and Computer Science Engineering undergraduate driven by a desire to understand how complex machines function from the silicon layer upward. Rather than treating microprocessors and computing systems as abstractions, my work starts at the physical boundary where voltage levels, magnetic induction, and microsecond timing constraints dictate execution.

My engineering builds range from hand-winding 1000:1 toroidal current transformer cores and designing discrete analog front-ends for 230V AC True-RMS sensing, to architecting deterministic FreeRTOS firmware that pins jitter-critical 32-bit I2S audio DMA synthesis to dedicated hardware cores. I thrive in the constraints of real hardware—where electrons produce noise, memory is bounded, and latency is physically measured.

On the software horizon, I combine low-level C++ with competitive algorithmic problem-solving and edge intelligence—engineering 60 FPS skeletal gesture tracking pipelines, coordinate Kalman filtering, and multimodal speech-vision architectures. The guiding principle behind every system I assemble is clear: bridge tangible physical physics with elegant mathematical computation.

// PROCESS ARCHITECTURE

ENGINEERING DNA

HOW A SYSTEM MOVES FROM FIRST-PRINCIPLES PHYSICS TO PRODUCTION
01

FIRST PRINCIPLES

Deconstruct Maxwell's equations, thermal dissipation limits, and signal-to-noise ratio.

→
02

SCHEMATIC & MATH

Derive transfer functions, burden resistances, Simpson's rule integrals, and algorithmic bounds.

→
03

BARE-METAL KERNEL

Write deterministic C++, configure DMA ring buffers, pin FreeRTOS tasks, and isolate interrupts.

→
04

BENCH TESTING

Probe with digital oscilloscopes, calibrate ADC DC-bias offsets, and profile microsecond execution jitter.

→
05

DEPLOY & HARDEN

Deploy closed-loop telemetry, implement fail-safe galvanic trip interlocks, and benchmark 60 FPS performance.

// PHYSICAL CRAFT & DISCIPLINE

BEYOND THE CODE

○
Toroidal Magnetic Winding: The tactile focus of hand-winding 1000 turns of fine enameled copper magnet wire onto miniature ferrite cores with uniform tension.
○
Electro-Acoustic Horology: Fascination with mechanical pendulum clocks, acoustic chime physics, and synthesizing Westminster bell harmonics through 32-bit DACs.
○
Daily Algorithmic Rigor: Treating competitive DSA problem-solving as daily mental fitness—reasoning through graph traversals, memoization bounds, and edge cases.
// EXTERNAL SIGNALS

VERIFIED REPOSITORIES & PROFILES

GITHUB Open-source firmware, AC power monitoring, audio synthesis & computer vision
@saptarshidas578 ↗
LEETCODE Competitive DSA problem solving with continuous LeetPush GitHub automation
@Saptarshi2007 ↗
LINKEDIN Professional engineering network, academic background & technical milestones
Saptarshi Das ↗
ONE SYSTEM ARCHITECTURE • DIVERSIFYING INTO PHYSICAL BUILDS
// 03 — BUILD ARCHIVE

SELECTED BUILDS

Physical prototypes, custom analog front-ends, bare-metal kernels, and real-time computer vision engines engineered from first principles. Each system is documented with verified schematics, circuit derivations, and measured benchmarks.

IDENTIFIER BUILD // 01 • FEATURED
STATUS BENCH TESTED & DEPLOYED
DOMAIN POWER ELECTRONICS • EMBEDDED DSP
TIMELINE 2026
CORE HARDWARE ESP32 • 1000:1 TOROIDAL CT • 25A OPTO-SSR
POWER TELEMETRY • SUB-CYCLE SAFETY INTERLOCK

INTELLIGENT SMART GRID & AC SENSING SYSTEM

A non-invasive 230V AC mains energy monitor and autonomous appliance safety interlock. Employs a hand-wound 1000:1 toroidal current transformer with active 1.65V DC-bias op-amp wave-shifting, computing true-RMS current via numerical Simpson's integration with sub-cycle overcurrent and thermal relay tripping.

Intelligent Smart Grid CT Coil and Analog Front-End Blueprint
SCHEMATIC: TOROIDAL CT (1000:1) • 68.2Ω BURDEN • 2.5 kV GALVANIC ISOLATION • ACTIVE 1.65V DC BIAS
01 // THE PROBLEM

Sustained 16A AC compressor loads generate severe resistive heat dissipation in conventional inline shunts (P = I²R). Meanwhile, non-isolated sensors expose 3.3V MCU digital rails to catastrophic mains spikes, high-voltage transients, and ground loops during line switching.

02 // THE APPROACH

Hand-wound high-permeability 1000:1 toroidal ferrite core steps 16A down to safe milliamps with 2.5 kV physical galvanic isolation. A precision 68.2Ω burden resistor and active 1.65V DC-bias op-amp front-end map the bipolar 50Hz sine wave into the unipolar 0–3.3V ADC range.

// SYSTEM ARCHITECTURE & SIGNAL FLOW HARDWARE INTERFACE PIPELINE
INPUT MAINS 230V 50Hz
→
SENSOR 1000:1 TOROIDAL CT
→
ANALOG FRONT-END 68.2Ω + 1.65V BIAS
→
MCU ADC ESP32 12-BIT ADC
→
FIRMWARE DSP SIMPSON'S TRUE-RMS
→
ACTUATOR OPTO-SSR TRIP (<18.5ms)
16.0 A CONTINUOUS RATED LOAD
< 18.5 ms SUB-CYCLE TRIP LATENCY
2.5 kV GALVANIC ISOLATION
98.8% ACCURACY (vs. FLUKE 87V)
• GITHUB REPOSITORY ↗
IDENTIFIER BUILD // 02
STATUS HARDWARE VERIFIED & RUNNING
DOMAIN ELECTRO-ACOUSTIC HOROLOGY • FREERTOS
TIMELINE 2026
CORE HARDWARE DUAL XTENSA @ 240MHz • TI PCM5100A I2S • DS1307 RTC
ESP32 Smart Grandfather Clock Architecture Blueprint
CORE 1 PINNED I2S • PCM5100A 32-BIT DAC • DS1307 BATTERY BACKUP
DUAL-CORE FREERTOS • 32-BIT I2S HARMONIC SYNTHESIS

ESP32 SMART GRANDFATHER CLOCK

Replaces traditional mechanical clock escapements with an ESP32 microcontroller synthesizing authentic multi-partial Westminster chimes. Dedicated FreeRTOS task pinning isolates 32-bit DMA audio streaming to Core 1, while Core 0 handles concurrent Wi-Fi NTP sync and DS1307 RTC fallback with 0.00 ms audio jitter.

// MULTI-CORE SIGNAL ARCHITECTURE
CORE 0 NTP / DS1307 / LED
•••
CORE 1 PINNED SYNTH TASK
→
DMA BUFFER CIRCULAR I2S DMA
→
I2S DAC PCM5100A 32-BIT
32-Bit I2S AUDIO DAC
0.00 ms AUDIO JITTER
< 20 ms DRIFT / WEEK
100% OFFLINE RTC FAILOVER
• GITHUB REPO ↗
IDENTIFIER BUILD // 03
STATUS BENCHMARKED ON GROQ LPUs
DOMAIN MULTIMODAL AI • COMPUTER VISION • LOW-LATENCY NLP
TIMELINE 2026
CORE STACK OPENAI WHISPER • MEDIAPIPE FACE MESH • GROQ LLAMA-3 70B
Multimodal AI Interview Assistant Pipeline Blueprint
468 3D FACIAL LANDMARKS • WHISPER STREAMING • GROQ LPU (285 T/S)
EDGE COMPUTER VISION • LOW-LATENCY MULTIMODAL PIPELINE

MULTIMODAL AI INTERVIEW ASSISTANT

An intelligent conversational coaching system. Integrates acoustic speech transcription via OpenAI Whisper with 468-point 3D facial landmark tracking (MediaPipe Face Mesh) to evaluate speech prosody, eye-contact percentage, and head pose. Pairs real-time multimodality with Groq LPU LLaMA-3 70B inference for sub-second adaptive technical feedback.

// MULTIMODAL INGESTION & INFERENCE PIPELINE
INPUT WEBCAM + MIC
→
VISION MESH MEDIAPIPE (468 PTS)
→
AUDIO ASR WHISPER STREAMING
→
LPU INFERENCE GROQ LLAMA-3 70B
285 t/s GROQ LPU SPEED
94.8% GAZE CONFIDENCE
< 120 ms AUDIO LATENCY
60 FPS CPU MESH TRACKING
• GITHUB REPO ↗
IDENTIFIER BUILD // 04
STATUS PRODUCTION BENCHMARKED
DOMAIN SPATIAL COMPUTING • HAND TRACKING • OCR
TIMELINE 2025 – 2026
CORE STACK PYTHON OPENCV • MEDIAPIPE HANDS • KALMAN/EMA • EASYOCR
Air Whiteboard Pro Gesture Tracking and OCR Blueprint
21-NODE SKELETAL TOPOLOGY • DUAL EMA FILTER (<0.4px) • EASYOCR TO LATEX
SPATIAL GESTURE COMPUTING • REAL-TIME MATHEMATICAL OCR

AIR WHITEBOARD PRO

A touchless spatial computing interface enabling users to write, sketch diagrams, and annotate math in mid-air using webcam input. Employs MediaPipe 21-node hand landmark topology with velocity-adaptive Exponential Moving Average (EMA) and Kalman filtering to eliminate camera noise, and integrates EasyOCR to parse drawn equations directly into LaTeX.

// SPATIAL GESTURE & OCR PROCESSING PIPELINE
INPUT WEBCAM (60 FPS)
→
TRACKING 21 HAND NODES
→
DSP FILTER DUAL EMA / KALMAN
→
OCR OUTPUT EASYOCR TO LATEX
< 0.4 px FILTERED JITTER
60 FPS CPU REAL-TIME
99.2% MATH OCR ACCURACY
< 8.2 ms STROKE LATENCY
• GITHUB REPO ↗
// 03 • BUILD ARCHIVE COMPLETE
FROM DISCRETE BUILDS TO ARCHITECTURAL FOUNDATIONS

Explore the underlying protocols, toolchains, microcontrollers, and neural frameworks powering these systems.

INSPECT ENGINEERING STACK ↓
// 04 — ARCHITECTURAL DEPENDENCIES

ENGINEERING STACK

Interactive constellation linking hardware electronics, bare-metal kernels, high-level algorithms, and edge intelligence. Hover any node to inspect protocols and real-world system applications.

INTERACTIVE NODE GRAPH • HOVER TECHNOLOGY NODES
TOOLS BECAME EXPERIMENTS • EXPERIMENTS BECAME SYSTEMS
// 05 — SYSTEM EVOLUTION

BUILD LOG

The progression from first-principles physics and circuit theory to bare-metal embedded kernels, intensive summer prototyping sprints, and real-time intelligent systems.

LAYER: TOP_SIG_L1 SUBSTRATE: FR-4 TG170 (1.6mm) COPPER: 2.0 OZ (70µm) FINISH: ENIG GOLD 99.9% IMPEDANCE: 50Ω DIFF IPC-6012 CLASS 3
FID1
FID2
FID3
FID4
TP1
⌜ ⌝ ⌞ ⌟
2025 — EARLY 2026
ACADEMIC INCEPTION • YEAR 1 U1 // CORE_PHYS

FIRST-PRINCIPLES FOUNDATIONS

Electrical & Computer Science Engineering • VIT Vellore

Began undergraduate studies at Vellore Institute of Technology (Class of 2029). Focused on deconstructing physics, circuit mathematics, and silicon mechanics from the ground up rather than treating microprocessors as black-box abstractions.

KEY COURSEWORK & THEORY:
Circuit Theory Multivariable Calculus Quantum Mechanics Digital Logic & Design Computer Architecture Analog Electronics Linear Algebra Python & Java OOP
VIT VELLORE MAXWELL'S LAWS ANALOG CIRCUITS LOGIC DESIGN
TP_VCC TP_LOGIC TP_GND
DIFF: 50Ω • SUBSTRATE: FR-4 • ENIG 99.9%
NET: CORE_PHYS
TP1B
⌜ ⌝ ⌞ ⌟
// EXHIBIT: SCHEMATIC CAD TOP_SILK • BGA BREAKOUT
PCB Schematic Foundations Layout
NETS: 142 ROUTED VIA_DENSITY: 88 FR-4 SUBSTRATE
TP2B
⌜ ⌝ ⌞ ⌟
// EXHIBIT: MULTI-LAYER EDA GPS02-UBX • HV STAGE
Multi-Layer EDA PCB Layout
2.5kV OPTO-ISOLATION CT: 1000:1 32-BIT I2S DMA
NET: CT_PWR
TP2
⌜ ⌝ ⌞ ⌟
MAY — JUNE 2026
INTENSIVE SUMMER SPRINT • PART I Q1 // PWR_STAGE

SILICON & REAL-TIME KERNELS

230V AC True-RMS Sensing • FreeRTOS Dual-Core Audio DMA

Transitioned from textbook schematic derivations into high-voltage bench experimentation and bare-metal firmware. Hand-wound a 1000:1 toroidal ferrite current transformer coil to measure continuous 16A loads with 2.5 kV galvanic isolation, deriving custom 68.2Ω burden resistors and active 1.65V DC-bias op-amp front-ends with sub-cycle (<18.5 ms) opto-isolated solid-state relay protection.

Concurrently mastered deterministic FreeRTOS task scheduling on dual-core Xtensa microcontrollers. Solved Wi-Fi preemption audio underruns by pinning I2S DMA Westminster chime synthesis strictly to Core 1 feeding an external 32-bit PCM5100A DAC with 0.00 ms jitter.

TOROIDAL CT COIL SIMPSON'S TRUE-RMS FREERTOS CORE PINNING 32-BIT I2S DAC
TP_230V TP_I2S_CLK TP_OPTO_ISO
ISOLATION: 2.5 kV • JITTER: 0.00ms
TP3
⌜ ⌝ ⌞ ⌟
JUNE — JULY 2026
INTENSIVE SUMMER SPRINT • PART II U2 // VISION_NPU

EDGE AI & SPATIAL COMPUTING

Low-Latency Multimodal Telemetry • Kalman Gesture Pipelines

Expanded from bare-metal C++ into real-time computer vision and edge intelligence. Engineered the Multimodal AI Interview Assistant, coupling streaming OpenAI Whisper speech chunks and local 468-point 3D facial mesh gaze calculations (60 FPS on CPU) with Groq LPU LLaMA-3 70B inference operating at 285 tokens/sec.

To solve high-frequency webcam hand tremor (±5 px jitter) in contactless spatial writing, developed Air Whiteboard Pro with a dual Exponential Moving Average (EMA) and velocity-adaptive Kalman filter, suppressing noise below 0.4 px while integrating EasyOCR for automatic mid-air math-to-LaTeX transcription.

OPENAI WHISPER MEDIAPIPE 468-PT MESH GROQ LPUs (285 T/S) KALMAN FILTER EASYOCR LATEX
TP_AUDIO_IN TP_60FPS_SYNC TP_GROQ_LPU
LATENCY: 285 T/S • NOISE: <0.4px
NET: NPU_DSP
TP3B
⌜ ⌝ ⌞ ⌟
// EXHIBIT: NEURAL SILICON ART ENIG 99.9% • HUMAN-AI
Neural Silicon Convergence PCB Art
468-PT MESH GAZE GROQ LPU: 285 T/S KALMAN <0.4px
TP4B
⌜ ⌝ ⌞ ⌟
// EXHIBIT: ALGORITHMIC MATRIX DENSE ROUTING
High-Density Algorithmic Circuit Routing
100+ LEETCODE DSA CLOSED-LOOP CTRL CORE 0+1 ACTIVE
NET: RTOS_ACT
TP4
⌜ ⌝ ⌞ ⌟
CURRENT STATE • 2026+
ACTIVE PRODUCTION • YEAR 2 MCU // XTENSA_RTOS

CONTROL SYSTEMS & ALGORITHMIC RIGOR

2nd Year Undergrad at VIT Vellore • Hardware-AI Interfacing

Currently advancing through 2nd-year engineering coursework at VIT Vellore in Control Systems, Electrical Machines, and Artificial Intelligence. Maintaining daily algorithmic mental fitness on LeetCode with 100+ problems solved across Graphs, Dynamic Programming, and Binary Search Trees, continuously synchronized to GitHub via automated LeetPush.

ACTIVE TECHNICAL FOCUS:

Bridging custom analog front-ends and electrical machine telemetry with closed-loop control algorithms and low-latency edge AI models.

CONTROL SYSTEMS ELECTRICAL MACHINES 100+ LEETCODE DSA EDGE HARDWARE AI
TP_CTRL_LOOP TP_DSA_PULL TP_LIVE_UPLINK
STATUS: CONTINUOUS EXECUTION • CORE 0+1
// 05 • BUILD LOG PERSISTED ──> DETECTING SYSTEM SIGNALS
VERIFIED OBSERVABLE EVIDENCE

Independent repository code, continuous problem-solving pipelines, and accredited certifications backing the systems.

INSPECT SIGNALS & ACHIEVEMENTS ↓
// 06 — SYSTEM SIGNALS • VERIFIED EVIDENCE

SIGNALS & ACHIEVEMENTS

Restrained, verifiable evidence backing the engineering narrative. Code repositories, competitive algorithmic milestones, accredited coursework, and academic foundations.

SYSTEM_STATUS: STEADY_STATE_EMITTING
SIGNAL_INTEGRITY: 100% VERIFIED
PROTOCOL: PUBLIC_REPOSITORIES • LEETPUSH • VIT
⌜ ⌝ ⌞ ⌟
// VECTOR 01 SOURCE REPOSITORIES
VERIFIED
saptarshidas578
13 PUBLIC REPOSITORIES
C • C++ • PYTHON PRIMARY LANGUAGES

Open-source embedded systems firmware, FreeRTOS audio pipelines, high-voltage sensor conditioning circuits, and machine learning models.

OPEN REPOSITORIES ↗
⌜ ⌝ ⌞ ⌟
// VECTOR 02 ALGORITHMIC RIGOR
VERIFIED
Saptarshi2007
100+ PROBLEMS SOLVED
LEETPUSH PIPELINE AUTOMATED GIT SYNC

Continuous practice across Graphs (Dijkstra, DFS/BFS), Dynamic Programming, Binary Search Trees, and Heaps with automated continuous GitHub integration.

VERIFY LEETCODE ↗
⌜ ⌝ ⌞ ⌟
// VECTOR 03 PROFESSIONAL IDENTITY
VERIFIED
saptarshi-das
VIT VELLORE (CLASS OF 2029)
EE • SYSTEMS CORE FOCUS

Academic milestones, engineering connections, hardware development updates, and public certification credentials.

VIEW PROFILE ↗
// VERIFIED CREDENTIALS & MILESTONES AUTHENTIC RECORD
2026 PROFESSIONAL CERTIFICATION

Developing AI Applications with Python & Flask • Embedded AI

IBM Developer Skills Network • Coursera

Engineered and validated Python Flask microservices incorporating Watson emotion detection models, packaging endpoints with unit tests and server routing.

INSPECT REPO ↗
2026+ PROBLEM SOLVING

100+ LeetCode Solutions with Automated Git Pipeline

LeetCode • Automated LeetPush Sync

Continuous algorithmic problem-solving repository with automated GitHub synchronization, cataloging Python 3 implementations across Graphs, Trees, and Dynamic Programming.

VIEW SOLUTIONS ↗
2026 OPEN SOURCE SYSTEM

Dual-Core ESP32 Smart Horology with FreeRTOS & I2S DMA Engine

Public GitHub Release

Architected deterministic real-time audio synthesis firmware in C on Xtensa dual-core architecture, achieving 0.00 ms audio jitter with NTP sync and hardware RTC backup.

VIEW FIRMWARE ↗
2025 — 2029 ACADEMIC PROGRAM

B.Tech Electrical & Computer Science Engineering

Vellore Institute of Technology (VIT), Vellore

Undergraduate program emphasizing Maxwell's equations, circuit theory, analog electronics, digital logic design, computer architecture, and linear algebra.

VIEW COURSEWORK →
REGISTRY ACCREDITED REGISTRY

Coursera Technical Coursework & Specialization Credentials

Coursera • LinkedIn Credential Records

Accredited digital certifications in AI development, computer science, and software engineering verified through institutional partners.

VERIFY CERTIFICATES ↗
// 06 • SIGNALS PERSISTED ──> SYSTEM CONVERGING TO IDLE STATE
CHANNEL OPEN // SYSTEM READY FOR TRANSMISSION

THE NEXT SYSTEM
STARTS WITH A CONVERSATION.

Available for bare-metal firmware architectures, analog signal acquisition, competitive algorithmic design, and low-latency multimodal edge AI research.

// PRIMARY DIRECT CHANNEL
// EXTERNAL CHANNELS
01 GITHUB ARCHIVE saptarshidas578 02 LINKEDIN NETWORK saptarshi-das 03 LEETCODE VERIFIED Saptarshi2007
DIRECT 256-BIT CHANNEL • TIMEZONE: IST (UTC+5:30) • LATENCY < 15ms
// FIRST TOUCH // VISUAL TRANSMISSION ファーストタッチ
STELLAR HARMONICS • ACTIVE TRANSMISSION
“THE SYSTEM IS COMPLETE. THE CHANNEL IS OPEN.”